Everything about Verifiable totally explained
In the context of hardware and software systems,
formal verification is the act of
proving or disproving the
correctness of intended
algorithms underlying a system with respect to a certain formal specification or property, using
formal methods of
mathematics.
Explanation
Software testing alone can't prove that a system doesn't contain any defects. Neither can it prove that it does have a certain property. Only the process of
formal verification can prove that a system doesn't have a certain defect or does have a certain property. It is impossible to prove or test that a system has "no defect" since it's impossible to formally specify what "no defect" means. All that can be done is prove that a system doesn't have any of the defects that can be thought of, and has all of the properties that together make it functional and useful.
Usage
Formal verification can be used for example for systems such as
cryptographic protocols,
combinational circuits,
digital circuits with internal memory, and software expressed as source code.
The verification of these systems is done by providing a formal proof on an abstract mathematical model of the system, the correspondence between the mathematical model and the nature of the system being otherwise known by construction. Examples of mathematical objects often used to model systems are:
finite state machines,
labelled transition systems,
Petri nets,
timed automata,
hybrid automata,
process algebra, formal semantics of programming languages such as
operational semantics,
denotational semantics,
axiomatic semantics and
Hoare logic.
Approaches to formal verification
There are roughly two approaches to formal verification.
The first approach is
model checking, which consists of a systematically exhaustive exploration of the mathematical model (this is possible for finite models, but also for some infinite models where infinite sets of states can be effectively represented). Usually this consists of exploring all states and transitions in the model, by using smart and domain-specific abstraction techniques to consider whole groups of states in a single operation and reduce computing time. Implementation techniques include
state space enumeration, symbolic state space enumeration,
abstract interpretation,
symbolic simulation,
abstraction refinement.
The second approach is logical inference. It consists of using a formal version of mathematical reasoning about the system, usually using theorem proving software such as a
HOL theorem prover, the
ACL2 theorem prover or the
Isabelle theorem prover. This is usually only partially automated and is driven by the user's understanding of the system to validate.
The properties to be verified are often described in
temporal logics, such as
linear temporal logic (LTL) or
computational tree logic (CTL).
Validation and Verification
Verification is one aspect of testing a product's fitness for purpose.
Validation is the complementary aspect. Often one refers to the overall checking process as V & V.
- Validation: "Are we trying to make the right thing?", for example, does the product do what the user really requires?
- Verification: "Have we made what we were trying to make?", for example, does the product conform to the specifications?
The verification process consists of static and dynamic parts. E.g., for a software product one can inspect the source code (static) and run against specific test cases (dynamic). Validation usually can only be done dynamically, for example, the product is tested by putting it through typical usages and atypical usages ("Can we break it?"). See also
Verification and ValidationFurther Information
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